1. Field of the Invention
The present invention relates to a routing method, and more particularly, to a method for dynamically arranging interrupt pins.
2. Description of Related Art
Interrupt Request (IRQ) is used for informing and requiring a processor to suspend the operation when a certain device intends to perform a specific action, so as to execute a corresponding calculation. The IRQ is sent through so-called interrupt lines, and the number of the interrupt lines varies depending on interrupt controllers adopted by the motherboard. A programmable interrupt controller (PIC) conventionally used in a computer includes 16 interrupt lines. However, these interrupt lines are still insufficient for the computer equipment with gradually powerful functions and gradually advanced input/output device, and most of the interrupt lines are occupied, or even shared by a plurality of hardware devices. Accordingly, some new motherboards adopt an advanced programmable interrupt controller (APIC), which can manage, generally, 24 IRQs (e.g., IOAPIC built in Intel ICHx and ESB2 series, herein some of them are used by message signal interrupts). Therefore, it can be used by many hardware devices, and can avoid sharing the interrupt lines.
If a PIC motherboard is used, only 4 interrupt lines can be used by PCI bus in practice. On the other aspect, if an APIC motherboard is used, 8 interrupt lines can be used. It indicates that even though the motherboard has 6 PCI shots, they can use only 4 or 8 IRQs. Moreover, accelerated graphics port (AGP), universal serial bus (USB), redundant array of independent disks (RAID) controller, and some onboard local area network (LAN) interfaces, 1394 interfaces and serial ATA (SATA) interfaces all should use IRQs. Under this circumstance, a plurality of PCI slots sharing one IRQ is unavoidable.
FIG. 1 is a hardware configuration diagram of a conventional PIC/IOAPIC motherboard. Referring to FIG. 1, the conventional PIC motherboard is disposed with a central processing unit (CPU) 110, Northbridge chip 120, Southbridge chip 130 and 4 PCI slots 140, 150, 160 and 170. The PCI slots 140, 150, 160 and 170 are used to transmit 4 interrupt messages INTA/INTB/INTC/INTD respectively to interrupt routing registers Rx_A, Rx_B, Rx_C and Rx_D (x=1,2,3,4) on the Northbridge chip 120. Since the PIC motherboard only supports 4 IRQs, when the Northbridge chip 120 transmits interrupt messages to the Southbridge chip 130, the PCI slots 140, 150, 160 and 170 share the 4 interrupt lines to sent the interrupt messages. The Southbridge chip 130 receives the interrupt messages transmitted by the Northbridge chip 120 via 4 interrupt router registers RA, RB, RC and RD respectively. The interrupt messages are then sent to a programmable interrupt controller (8259 PIC), and then, the 8259 PIC sends an IRQ to the CPU 110. It should be noted that, the conventional IOAPIC motherboard has an additional IOAPIC compared with the PIC motherboard, and sends the IRQ to the CPU 110 via the 8259 PIC and the IOAPIC.
FIG. 2 shows a configuration table of the routing for conventional interrupt pins. Referring to FIG. 2, the pins A, B, C, D of each PCI slot respectively correspond to different interrupt messages INTA/INTB/INTC/INTD, and the Basic Input/Output System (BIOS) also arranges the IRQs for being used or shared corresponding to different interrupt messages INTA/INTB/INTC/INTD when executing the Power-On Self Test (POST). For example, the pins A, B, C, D of slot #2 correspond to the interrupt messages INTA/INTB/INTC/INTD, and thus when arranging the IRQs, numbers of 4, 1, 2, 3 are stored in the corresponding interrupt router registers R2_A, R2_B, R2_C and R2_D according to the sequence, so as to trigger the IRQ through the interrupt pins 4, 1, 2, 3 of the IOAPIC.
If the 4 PCI slots all have one PCI interface card inserted therein, and each PCI interface card requires to trigger 4 interrupts respectively through the interrupt pins 1, 2, 3, 4, there are 4 hardware devices shared on each IOAPIC interrupt line, and 4 hardware drivers are required to be connected in series to the 4 interrupt lines. Accordingly, in such a circumstance, the sharing status of each IOAPIC interrupt line is the same, which is the optimized situation.
The above method is suitable for arranging PCI slots on the basis that the frequencies of the interrupts sent by the PCI devices disposed on each PCI slot are almost the same. However, in practical application, the numbers of interrupts sent by different PCI devices in a unit time are different, that is, some PCI devices are very busy, whereas some PCI devices are rather idle. This characteristic still causes the arrangement of interrupt pins to be non-uniform, and thus, the conventional technique is not the optimum arranging manner.